1. Field of the Invention
The present invention relates in general to a servo motor control circuit for a servo system of a video signal recording/playback apparatus, and more particularly to a servo motor control circuit for attenuating a gain of a transfer signal increased at a low-frequency region using a low-frequency gain attenuation filter to control a servo motor.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional servo motor control circuit. As shown in this drawing, the conventional servo motor control circuit comprises a pulse generator 2 for generating a pulse signal according to a rotation of a servo motor M 1, a wave-shaping circuit 3 for wave-shaping an output signal a from the pulse generator 2 and outputting the resultant two signals b and c, a speed error detector 3' for inputting the output signals c and b from the wave-shaping circuit 3 as reset and enable signals, respectively, and counting an external clock signal CK1 in response to the inputted signals to output a speed error signal e, a first filtering circuit 4 for filtering a torque ripple component of the speed error signal e from the speed error detector 3' in response to the output signal b from the wave-shaping circuit 3, and a multiplier 5 for multiplying an output signal n from the first filtering circuit 4 by a desired number. The output signals b and c from the wave-shaping circuit 3 are generated out of phase with each other.
The conventional servo motor control circuit also comprises a phase error detector 6 for counting an external clock signal CK2 in response to the output signal b from the wave-shaping circuit 3 to output a phase error signal i in response to an external vertical synchronous signal h, a second filtering circuit 7 for filtering the phase error signal i from the phase error detector 6 at a desired frequency band in response to the vertical synchronous signal h, a speed/phase adder 8 for adding an output signal from the multiplier 5 and an output signal from the second filtering circuit 7, and a motor controller 9 for controlling the servo motor 1 in response to an output signal from the speed/phase adder 8 and the output signal b from the wave-shaping circuit 3.
Referring to FIG. 2, there is shown a detailed block diagram of the first filtering circuit 4. As shown in this drawing, the first filtering circuit 4 includes a first adder 4a for adding the speed error signal e from the speed error detector 3' and a delayed signal Z, an adding range limiter 4b for limiting a desired range of an output signal from the first adder 4a, a first delay 4c for delaying an output signal from the adding range limiter 4b for a predetermined time period in response to the output signal b from the wave-shaping circuit 3; a second delay 4d for delaying an output signal from the first delay 4c for the predetermined time period in response to the output signal b from the wave-shaping circuit 3 and outputting the delayed signal Z to the first adder 4a, a multiplier 4e for multiplying the output signal from the first delay 4c by a desired number, and a second adder 4f for adding an output signal m from the multiplier 4e and the speed error signal e from the speed error detector 3'.
Referring again to FIG. 1, the phase error detector 6 includes a frequency divider 6a for frequency-dividing the output signal b from the wave-shaping circuit 3 at a desired ratio, and a counter 6b being reset in response to an output signal f from the frequency divider 6a to count the clock signal CK2 and output the resultant signal as the phase error signal i in response to the vertical synchronous signal h.
The motor controller 9 includes a third filtering circuit 9a for filtering the output signal from the speed/phase adder 8 at a desired frequency band in response to the output signal b from the wave-shaping circuit 3, a digital/analog converter 9b for converting a digital signal from the third filtering circuit 9a into an analog signal, and a motor driver 9c for driving the servo motor 1 in response to an output signal from the digital/analog converter 9b.
The operation of the conventional servo motor control circuit with the above-mentioned construction will hereinafter be described with reference to FIGS. 3A to 5. FIGS. 3A to 3N are waveform diagrams of the signals from the components in FIGS. 1 and 2, FIG. 4 is a graph illustrating a signal transfer characteristic in FIG. 2, and FIG. 5 is a graph illustrating a signal gain characteristic in FIG. 1.
First, as the servo motor M 1 is rotated, the pulse generator 2 generates a sinusoidal wave pulse signal a as shown in FIG. 3A and outputs the generated sinusoidal wave pulse signal a to the wave-shaping circuit 3. Upon receiving the sinusoidal wave pulse signal a from the pulse generator 2, the wave-shaping circuit 3 wave-shapes the received sinusoidal wave pulse signal a and outputs the resultant square wave pulse signals b and c as shown in FIGS. 3B and 3C to the speed error detector 3'. The square wave pulse signal b from the wave-shaping circuit 3 is also applied to the first and second delays 4c and 4d in the first filtering circuit 4, the frequency divider 6a in the phase error detector 6 and the third filtering circuit 9a in the motor controller 9.
The speed error detector 3' is reset in response to the square wave pulse signal c from the wave-shaping circuit 3 and enabled in response to the square wave pulse signal b from the wave-shaping circuit 3. As a result, the speed error detector 3' counts the clock signal CK1, as shown in FIG. 3D, and outputs the resultant speed error signal e as shown in FIG. SE.
The speed error signal e from the speed error detector 3' is applied to the first and second adders 4a and 4f in the first filtering circuit 4.
Then in the first filtering circuit 4, the first adder 4a adds the speed error signal e from the speed error detector 3' and the delayed signal Z from the second delay 4d and outputs the resultant signal to the adding range limiter 4b. The adding range limiter 4b limits the desired range of the output signal from the first adder 4a and outputs the resultant signal to the first delay 4c.
The first delay 4c shifts the output signal from the adding range limiter 4b for the predetermined time period in response to the output signal b from the wave-shaping circuit 3 and outputs the resultant signal to the second delay 4b and the multiplier 4e.
Upon receiving the output signal from the first delay 4c, the second delay 4d shifts the received signal for the predetermined time period in response to the output signal b from the wave-shaping circuit 3 and outputs the resultant signal Z to the first adder 4a.
Thereafter, the first adder 4a, the adding range limiter 4b and the first and second delays 4c and 4d perform repeatedly the above sequential operation.
On the other hand, the multiplier 4e multiplies the output signal from the first delay 4c by the desired number K and outputs the resultant pulse signal m as shown in FIG. 3M to the second adder 4f. The second adder 4f adds the output signal m from the multiplier 4e and the speed error signal e from the speed error detector 3' and outputs the resultant signal n as shown in FIG. 3N to the multiplier 5.
Noticeably, the first filtering circuit 4 acts to remove the torque ripple component generated in the rotation of the servo motor 1. In the signal transfer characteristic of the first filtering circuit 4, as shown in FIG. 4, a gain of the output signal n is infinite at a low frequency band.
Here, a Z-transform value of the adding range limiter 4b is Z.sup.-M, a Z-transform value of the first delay 4c is Z.sup.d and a Z-transform value of the second delay 4d is Z.sup.-d. As a result, a transfer function T.sub.f of the first filtering circuit 4 can be expressed by the following equation (1): EQU T.sub.f =1+[(Z.sup.-M .multidot.Z.sup.d .multidot.K)/(1-Z.sup.-M)](1)
FIG. 3K shows a waveform of the speed error signal which is again applied from the speed error detector 3' to the first filtering circuit 4 after the above filtering operation is performed by the first filtering circuit 4.
Then, upon receiving the output signal n from the second adder 4f in the first filtering circuit 4, the multiplier 5 multiplies the received signal n by the desired number and outputs the resultant signal to the speed/phase adder 8.
On the other hand, in the phase error detector 6, the frequency divider 6afrequency-divides the output signal b from the wave-shaping circuit 3 by 10 and outputs the resultant signal f as shown in FIG. 3F to the counter 6b. The counter 6b is reset in response to the output signal f from the frequency divider 6a, so as to count the clock signal CK2, as shown in FIG. 3G.
Upon receiving the vertical synchronous signal h as shown in FIG. 3H in the counting operation, the counter 6b outputs the phase error signal i as shown in FIG. 3I to the second filtering circuit 7.
The second filtering circuit 7 filters the phase error signal i from the counter 6b in the phase error detector 6 at the desired frequency band in response to the vertical synchronous signal h and outputs the resultant signal to the speed/phase adder 8.
Then, the speed/phase adder 8 adds a speed value or the output signal from the multiplier 5 and a phase value or the output signal from the second filtering circuit 7 and outputs the resultant value to the motor controller 9.
As seen from FIG. 5, a phase system gain PC or a gain of the output signal from the second filtering circuit 7 is not obtained as indicated by an ideal gain curve c but as indicated by a curve d. The sum AFPC of the phase system gain and a speed system gain or the sum of the gain of the output signal from the second filtering circuit 7 and a gain of the output signal from the multiplier 5 is not obtained as indicated by an ideal gain curve b but as indicated by a curve a.
Then in the motor controller 9, the third filtering circuit 9a filters the output signal from the speed/phase adder 8 at the desired frequency band in response to the output signal b from the wave-shaping circuit 3 and outputs the resultant digital signal to the digital/analog converter 9b. The digital/analog converter 9b converts the digital signal from the third filtering circuit 9a into the analog signal and outputs the converted analog signal to the motor driver 9c.
As a result, the motor driver 9c drives the servo motor 1 in response to the output signal from the digital/analog converter 9b.
However, the above-mentioned conventional servo motor control circuit has a disadvantage in that the phase system gain is reduced at the low frequency band because the gain of the output signal from the torque ripple removing filter is infinite at the low frequency band, resulting in a phase distortion at the low frequency band and a bad effect on a phase stabilization time. Namely, as the low-frequency speed system gain is increased, the sum of the phase system gain and the speed system gain is increased, whereas the low-frequency phase system gain is reduced. For this reason, the phase stabilization time is lengthened and the phase distortion is caused at the low frequency band.